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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-22410-1E
ASSP
COMMUNICATION CONTROL SCSI-2 PROTOCOL CONTROLLER
MB86603
DESCRIPTION
The MB86603 is a SCSI-2 protocol controller (SPC) that facilitates interface control between the host computer (medium/small) and peripheral devices. The specifications conform to the SCSI-2 standard but have an improved baud rate and extended functions. The MB86603 supports high-speed synchronous transfer, wide transfer (16 bits), the MPU/DMA stand-alone system bus, and programmable commands, to enable configuration of high-performance systems. The MB86603 (SPC hereafter) is applicable to both single-end and differential transmissions and has a driver/receiver that can drive single-end heavy current (48 mA). It can also have the phase-to-phase sequence control function to reduce the program overhead of the host MPU. For the abbreviations in this data sheet, see the next page.
FEATURES
SCSI Bus Interface
* Operable as initiator and target * Two types of data transfer
- Synchronous transfer: Max. 20 Mbytes/s, max. 32 offsets, 32-level baud rate - Asynchronous transfer: Max. 10 Mbytes/s
* Transfer parameters (transfer mode, baud rate, transfer offset for 15 connected devices) * Single-end and differential transmissions
Driver/receiver capable of driving 48-mA single-end heavy current
* Tristate bidirectional buffers for transfer control signals (REQ, ACK)
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176-Lead Plastic SQFP Package FPT-176P-M01
Copyright
(c)1994 by FUJITSU LIMITED
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MB86603
Transfer Operation
* Automatic response to selection/reselection
Prespecified receiving performed automatically at selection or reselection Initiator: Automatically responds to reselection from target and operable until message received Target: Automatically responds to selection from initiator and can operate until command received
* Automatic receiving
Initiator: Can automatically receive information for new phase to which target shifted Target: Can perform automatic receiving in response to attention condition generated by initiator
* 64-byte data register (FIFO) for data phase * Two (send-only and receive-only) 32-byte memory data buffers for message, command, and status phases * 16-bit transfer block and 24-bit transfer byte registers enabling 1Tbyte transfer (1Tbyte: * Independent data transfer bus enabling microprocessor to operate during data transfer * Selection between parity through and generate
System Bus Interface 16 Mbytes x 64 Kblocks)
* 16-bit MPU/DMA stand-alone system bus * Direct connection with 68 series/80 series 16-bit MPUs * Two types of transfer
Program transfer DMA transfer (burst mode) Commands
* Sequential command for sequential operation and programmable command for programming, including ordinary commands * Command queuing
Commands can be tagged in the command phase for continuous issuing.
* 512-byte memory as command program memory and command queue buffer
Others
* CMOS * System clock frequency: * +5 V single power supply
SCSI-2: Enhanced Small Computer System Interface ANSI: American National Standard Institute SPC: SCSI-2 Protocol Controller MPU: Micro-Processing Unit DMA: Direct Memory Access FIFO: First-In First-Out ID: Identifier (identification number assigned to each device connected to SCSI bus) 80 series: General term for MPU based on command system of 8080A developed by Intel 68 series: General term for MPU developed by Motorola 12 MHz to 32 MHz
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MB86603
PIN ASSIGNMENT
RSTOE BSYOE VDD ATN (NC) SELOE VSS (NC) BSY RET (NC) ACK (NC) VSS (NC) SEL (NC) MSG (NC) C/D VSS (NC) REQ VDD (NC) I/O (NC) VSS (NC) DB8 DB10 (NC) DB9 VSS (NC) DB11 TARG (NC) TEST2 VSS DBOE8 INIT (OPEN) (OPEN)
130
125
120
115
110
105
100
95
90
VSS A0 A1 A2 A3 A4 CS0 CS1 LDP VSS D0 VDD D1 D2 D3 D4 D5 D6 D7 VSS VDD (NC) D8 D9 D10 D11 D12 (NC) D13 D14 D15 UDP VSS (NC) BHE WR VDD RD INT MODE RESET LDBOEP DBOE7 (NC) 1 5 10 15 20 25 30 35 40 175 45 170 50 165 55 160 155 65 150 70 145 75 140 80 135 85
(NC) DBOE9 DBOE10 DBOE11 DBOE12 TP DREQ DACK (NC) DMBHE CLK VDD UDMDP VSS DMD15 DMD14 DMD13 VDD DMD12 DMD11 DMD10
(TOP VIEW)
60
DMD9 DMD8 VSS DMD7 DMD6 DMD5 DMD4 DMD3 DMD2 VDD DMD1 DMD0 VSS LDMDP DMA0
INDEX
(NC) IOWR IORD S/DSEL DBOE13 DBOE14 DBOE15 VSS
(NC) DBOE6
VSS DBOE4
LDBP VSS
DB7 DB6
DB5 VSS
DB4 (NC)
(NC) DB2
VSS (NC)
DB1 DB0
UDBP (NC)
(NC) DB15
(NC) DB13
(NC) DB12
DBOE2
UDBOEP VDD
DBOE1 DBOE0
DBOE5
(NC)
(NC)
(NC)
(NC)
DB3
VDD
(NC)
(NC)
VSS
DB14
VSS
DBOE3
(FPT-176P-M01)
3
MB86603
BLOCK DIAGRAM
D15 to D7 to D8, D0, INT UDP LDP WR SCSI Interface MPU interface MSG C/D I/O ATN BSYOE BSY 2 SELOE SEL RSTOE RST REQ ACK INIT TARG 8 (512 bytes) User program memory 3 Phase controller 7 Transfer controller Timer 6 (32 bytes) Receive MSG, CMD, Status buffer DMA Interface DREQ DACK DMBHE (32 bytes) Send MSG, CMD, Status buffer DMA0 1 Internal processor 5 Various registers
RD
CS0
CS1
A4 to A0
BHE
MODE
4
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP
DB15 to DB8, UDBP DB7 to DB0, LDBP 9 DBOE15 to DBOE8, UDBOEP DBOE7 to DBOE0, LDBOEP S/DSEL
IOWR IORD
Data register (64 bytes)
T.P.
4
MB86603
BLOCK DESCRIPTION
1. Internal processor (sequensor)
This processor provides sequence control between each phase.
Bus-free phase
Information-transfer phase
Information-transfer phase * Command phase * Data phase * Status phase * Message phase
Arbitration phase
Selection phase
2. Timer
This timer manages timing specified by the SCSI and the following timing.
* REQ/ACK assertion time for data at asynchronous transfer * Selection/reselection retry time * Selection/reselection timeout time * REQ/ACK timeout time during transfer
Asynchronous transfer (target): Time required for initiator to assert ACK signal after asserting REQ signal Asynchronous transfer (initiator): Time required for target to negate REQ signal after asserting ACK signal Synchronous transfer (target only): Time required for target to send REQ signal and then receive ACK signal for setting offset to 0 from initiator
3. Phase Controller
This controller controls the arbitration, selection/reselection, data in/out, command, status, and message in/out phases executed on the SCSI bus.
4. Transfer Controller
This controller controls the information (data, command, status, message) transfer phase executed on the SCSI bus. There are two transfer types for executing the information transfer phase.
* Asynchronous transfer: Control by interlocking REQ and ACK signals * Synchronous transfer: Control with maximum of 32-byte offset value in data in/out phase
There are two types of modes depending on the data movement as follows:
* Program transfer: Performed via MPU interface using data registers * DMA transfer: Performed via DMA interface using DREQ and DACK pins
At synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of REQ or ACK signal sent from SPC in synchronous transfer, and maximum REQ/ACK offset value in synchronous transfer) can be saved for each ID and automatically set when the data phase is started. The transfer byte count is determined by block length x number of blocks.
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MB86603
5. Various Registers
The main registers are as follows:
* Command register
This register specifies each command with an 8-bit code. If the user program is used, the starting address of the program assigned to the user program memory is specified.
* Nexus status register
This register indicates the chip's operating condition, linked partner's ID, and data register status.
* SCSI control signal status register
This register indicates the status of the SCSI control signals.
* Interrupt status register
This register indicates the interrupt status with an 8-bit code.
* Command step register
This register indicates the execution status of each command with an 8-bit step code. Referencing the interrupt status register and this register permits analysis of error causes.
* Group 6/7 command-length setting register
This register sets the group 6/7 command length not defined in the SCSI standard. Setting this register permits group 6/7-command length decisions.
6. Receive MSG, CMD, Status Buffer (RECEIVE MCS Buffer)
This is a 32-byte receive-only information buffer that holds the message, command, and status information received from the SCSI bus.
7. Send MSG, CMD, Status Buffer (SEND MCS Buffer)
This is a 32-byte send-only information buffer that holds the message, command, and status information sent on the SCSI bus.
8. User Program Memory
This is a 512-byte program memory that stores programmable commands. It consists of two 256-byte banks.
9. Data Register
This is a 64-byte FIFO-type data register that holds data when the data phase is executed on the SCSI bus.
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MB86603
PIN DESCRIPTION
1. SCSI Interface
There are two types of SCSI interface corresponding to two types of transmission systems; each type operates differently.
Pin No. 109
Pin Symbol REQ
Pin Name Request
I/O I/O
Function This is used for transfer request signals from the target to the initiator in the information-transfer phase. The input signal is used as a data transfer sequence timing control signal. The signal is Active Low. This is used for response signals from the initiator to the target in response to the REQ signal in the information-transfer phase. The input signal is used as a data transfer sequence timing control signal. The signal is Active Low. This is used for request signals for the message-transfer phase from the initiator to the target. The signal is Active Low. This is used for signals specifying the type of information transmitted on the data bus. The signal is Active Low and goes Low when specifying the message phase. This is used for signals for specifying the type of information transmitted on the data bus. The signal is Active Low and goes Low when specifying the command, status, and message phases. This is used for signals for specifying the transfer direction of information transferred on the data bus. The signal is Active Low. At Low, information is transferred from the target to the initiator. At High, information is transferred from the initiator to the target. This indicates that the SCSI bus is busy. In the arbitration phase, this pin is used for signals requesting bus acquisition. The signal is Active Low. This is used for input of signals that are output and detected by the initiator and target in the selection phase (the initiator selects the target) and reselection phase (the target reselects the initiator). The signal is Active Low. This is used for output of reset signals to other SCSI devices and for input of reset signals from other SCSI devices. The signal is Active Low. This is used for output control of BSY signals. In the differential mode, this pin should be used for control signals for the external differential driver/receiver. The signal is Active High. (Continued)
123
ACK
Acknowledge
I/O
127
ATN
Attention
I/O
117
MSG*
Message
I/O
113
C/D*
Controll/Date
I/O
107
I/O*
Input/Output
I/O
124
BSY
Busy
I/O
115
SEL
Select
I/O
121
RST
Reset
I/O
131
BSYOE**
Busy Output Enable
O
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MB86603
Pin No. 129 Pin Symbol SELOE** Pin Name Select Output Enable I/O O Function This is used for output control of SEL signals. In the differential mode, this pin should be used for control signals for the external differential driver/receiver. The signal is Active High. This is used for output control of RST signals. In the differential mode, this pin should be used for control signals for the external differential driver/receiver. The signal is Active High. These are bidirectional SCSI data buses made up of 2-byte data and each odd parity bit of the upper/lower byte.
130
RSTOE**
Reset Output Enable
O
32, 33, 35 38, 99, 100, 102, 105, 28, 10, 11, 13 16, 18, 20 25, 26, 7 46, 47, 48 84, 85, 86 87, 92, 43, 175, 2, 3, 5, 39, 40, 41, 42, 174 93 94 49
DB15 to DB8, UDBP, DB7 to DB0, LDBP
Data Bus 15 to Data Bus 8, Upper Data Bus Parity, Data Bus 7 to Data Bus 0, Lower Data Bus Parity
I/O
DBOE15 to Data Bus 15 to 8 Output Enable, DBOE8, UDBOEP, Upper Data Bus Output Enable Parity, DBOE7 to Data Bus 7 to 0 Output Enable, Lower DBOE0, LDBOEP** Data Bus Output Enable Parity INIT** *** Initiator
O
These are used for output control of DB15 to DB8, UDBP, DB7 to DB0, LDBP signals. In the differential mode, these pins should be used for control signals for the external differential driver/receiver. The signal is Active High.
O O I
TARG** *** Target S/DSEL** Single-End Differential Select
These are used for signals for indicating the operation or connection condition of the SPC. These pins should be used for control signals for the external differential driver/ receiver. The signal is Active High. This is used for input of signals for selecting the chip operation mode. SINGLE-ENDED: Enter -0. DIFFERENTIAL: Enter -1.
*The correspondence between the C/D, C/D, I/O signals and phase is given on the next page. **For the connection example of the external differential driver/receiver circuit, see SYSTEM CONFIGURATION, 5. ***The operation or connection condition of the SPC is given on the next page. Note: I/O pins for the SCSI interface can be connected directly to the single-end SCSI bus.
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MB86603
Transfer Direction Phase Name MSG C/D I/O Initiator Data-out phase Data-in phase Command phase Status phase Message-out phase Message-in phase H H H H L L H H L L L L H L H L H L Target

INIT L L H
TARG L H L Not connected to SCSI
Condition
Executing reselection phase or in connection as target Executing reselection phase or in connection as initiator
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MB86603
2. MPU Interface
Pin No. 139 140 Pin Symbol* CS0 CS1 Pin Name Chip Select 0 Chip Select 1 Data 15 to Data 8 Upper Data Parity Data 7 to Data 0 Lower Data Parity Address 4 to Address 0 Read (Read/Write) I I I/O I/O I I Function This is used for signals for the MPU to select the SPC as the I/O device. The signal is Active Low. This is used for select signals for the MPU to input and output DMA-bus data via the SPC. The signal is Active Low. These are used for the upper-byte and parity-bit signals of the data bus. When the CS0 input is valid, these pins serve as I/O ports for the registers in the SPC. When the CS1 input is valid, these pins serve as data I/O ports for the DMA bus. These are used for lower-byte and parity-bit signals of the data bus. When the CS0 input is valid, these pins serve as I/O ports for the registers in the SPC. When the CS1 input is valid, these pins serve as data I/O ports for the DMA bus. These are used to input addresses for selecting the internal register. In the 80-series mode, this is used for input of signals (IORD or RD) for the read operation from the SPC to the MPU. The signal is Active Low. In the 68-series mode, this is used for input of control signals (R/W) for the read and write operations from the MPU to the SPC. The signal is Active High at the read operation and Active Low at the write operation. In the 80-series mode, this is used for input of signals (IOWR or WR) for the write operation from the MPU to the SPC. In the 68-series mode, this is used for input of LDS signals output by the MPU when the lower bytes of the data bus are valid. The signal is Active Low in both modes. In the 80-series mode, this is used for input of BHE signals output by the MPU when the upper bytes of the data bus are valid. In the 68-series mode, this is used for input of UDS signals output by the MPU when the upper bytes of the data bus are valid. The signal is Active Low in both modes. This is used for output of interrupt request signals. In the 80-series mode, the signal is Active High. In the 68-series mode, the signal is Active Low. When SPC BSY = 1 (bit 6 of SPC status register = 1), this signal is not active. Therefore, this signal becomes inactive when a command is issued to the SPC at active, or when the SPC BSY goes to 1 after automatically starting the operation. This signal becomes inactive as soon as the first interrupt code is read, even if more than one interrupt is held. This is used to input signals specifying the type of MPU and DMA buses. A High level is input in the 80-series mode. A Low level is input in the 68-series mode.
163 to 161, 159 to 155 164 151 to 145, 143 141 138 to 134 170
D15 to D8 UDP D7 to D0 LDP A4 to A0 RD (R/W)
I/O
168
WR (LDS)
Write (Lower Data Strobe)
I
167
BHE (UDS)
Bus High Enable (Upper Data Strobe)
I
171
INT (INT)
Interrupt Request
O
172
MODE
Mode
I
*The pin symbols in parentheses are the ones when the MODE input is Low.
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MB86603
3. DMA Interface
Like the MPU interface, the DMA interface has input/output signals for the 68 series and 80 series.
Pin No. 82
Pin Symbol* DREQ
Pin Name DMA Request
I/O O
Function This is used for output of DMA transfer request signals to the DMA controller. A request is made for data transfer between the SPC and the memory over the DMA bus. The signal is Active High. This is used for input of DMA acknowledge signals from the DMA controller. When this input pin is active, the DMA cycle (read/write) is executed. The signal is Active Low. These are used for input and output of the upper-byte and parity signals of the DMA data bus. When the CS1 input is valid, these pins are connected directly to the MPU bus.
81
DACK
DMA Acknowledge
I
74 to 72, 70 to 66 76 64 to 59, 57, 56 54 50
DMD15 to DMD8 UDMDP DMD7 to DMD0 LDMDP IORD (DMR/W)
DMA Data 15 to DMA Data 8 Upper DMA Data Parity DMA Data 7 to DMA Data 0 Lower DMA Data Parity I/O Read (DMA Read/Write)
I/O
I/O
These are used for input and output of the lower-byte and parity signals of the DMA data bus. When the CS1 input is valid, these pins are connected directly to the MPU bus.
I
In the 80-series mode, this is used for input of signals (IORD or RD) for outputting data from the SPC to the DMA bus. The signal is Active Low. In the 68-series mode, this is used for input of control signals (DMR/W) for inputting and outputting data from the DMA controller to the SPC. The signal is Active High for output and Active Low for input. In the 80-series mode, this is used for input of signals (IOWR or WR) for inputting data from the DMA bus to the SPC. In the 68-series mode, this is used for input of LDS signals output by the DMA controller when the lower bytes of the DMA data bus are valid. The signal is Active Low in both modes. In the 80-series mode, this is used for input of BHE signals output by the DMA controller when the upper bytes of the DMA data bus are valid. In the 68-series mode, this is used for input of UDS signals output by the DMA controller when the upper bytes of the DMA data bus are valid. The signal is Active Low in both modes. In the 80-series mode, this is used for input of address data A0 signals output by the DMA controller. In the 68-series mode, this is connected to the power supply (VDD). This is used for input of DMA transfer permission signals. When this signal is active, the SPC performs the DMA transfer. When this signal becomes inactive during DMA transfer, transfer is temporarily stopped at the block boundary. The signal is Active High.
51
IOWR (DMLDS)
I/O Write (DMA Lower Data Strobe)
I
79
DMBHE (DMUDS)
DMA Bus High Enable (Upper Data Strobe)
I
53
DMA0
DMA Address 0
I
83
TP
Transfer Permission
I
*The pin symbols in parentheses are the ones when the MODE input is Low.
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MB86603
4. Others
Pin No. 173 Pin Symbol RESET Pin Name Reset I/O I Function This is used for input of system-reset signals. At input, the reset signals must be kept active for four or more clock cycles. The signal is Active Low. This is used for input of clock pulse signals. The clock frequency ranges from 12 MHz to 32 MHz. These are used for the +5 V power supply. --
78 21, 44, 58, 71, 77, 110, 132, 144, 153, 169 4, 8, 14, 22, 30, 36, 45, 55, 65, 75, 91, 97, 103, 111, 119, 125, 133, 142, 152, 165 96 89, 90 1, 6, 9, 12 15, 17, 19 23, 24, 27 29, 31, 34 37, 52, 80 88, 95, 98 101, 104 106, 108, 112, 114, 116, 118, 120, 122, 126, 128, 154, 160, 166, 176
CLK VDD
Clock I Power Supply
VSS
Ground --
These are used for grounding.
TEST2 (OPEN) (NC)
Test (Open) (Non Connection)
I -- --
Must be grounded Must be open. Do not connect. Not connected internally. As a general rule, do not connect.
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MB86603
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage* Input voltage* Output voltage* Operating ambient temperature Storage temperature *The voltages are based on VSS (= 0 V). Note: Permanent device damage may occur if the above ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol VDD VI VO Top Tstg Rating VSS - 0.5 to +6.0 VSS - 0.5 to VDD + 0.5 VSS - 0.5 to VDD + 0.5 -25 to + 85 -40 to + 125 Unit V V V
C C
RECOMMENDED OPERATING CONDITIONS
Requirements Parameter Supply voltage* RESET Non-SCSI pins High-level input voltage* SCSI pins Low-level input voltage* Non-SCSI pins REQ, ACK High-level output current** SCSI pins In single-end mode Others In differential mode Non-SCSI pins Low-level output current** SCSI pins Operating ambient temperature TA IOL -- 0 -- -- +48 +70 mA IOH VIL Others VIH 2.2 2.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.8 -2.0 -8.0 -- -8.0 +3.2 V V V mA mA mA mA mA Symbol Min. VDD 4.75 2.4 Typ. 5.0 -- Max. 5.25 -- V V Unit
C
*The voltages are based on VSS (= 0 V). **SCSI pins can be UDBP, DB15, to DB8, LDBP, DB7 to DB0, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, and I/D pins. Note: The recommended operating conditions are the recommended values for assuring normal logic operation of the LSI. Requirements in electrical characteristics (DC and AC characteristics) are assured within the range of the recommended operating conditions.
13
MB86603
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VDD = 5 V 5%, VSS = 0 V, TA = 0C to +70C) Parameter RESET Non-SCSI pins High-level input voltage* SCSI pins Low-level input voltage SCSI-pin input hysteresis Non-SCSI pins REQ, ACK High-level output voltage* SCSI pins In differential mode Non-SCSI pins Low-level output voltage SCSI pins Input leakage current Input/output leakage current** Supply voltage ILI ILOZ VOL In single-end mode Others VOH VIL VHW -- -- IOH = -2.0 mA IOH = -8.0 mA -- IOL = -8.0 mA IOL = +3.2 mA IOL = +3.2 mA IOL = +48.0 mA VIN = 0 to VDD VIN = 0 to VDD Output open Clock: 32 MHz (operating) Others VIH -- 2.2 2.0 -- 0.2 4.2 2.5 -- 2.5 VSS VSS -- -10 -10 -- -- 0.8 -- VDD -- -- -- 0.4 0.4 0.5 +10 +10 V V V V V V V V V V V Symbol Measurement Conditions Requirements Unit Min. 2.4 Max. -- V
A
IDD
--
70
mA
*SCSI pins can be UDBP, DB15, to DB8, LDBP, DB7 to DB0, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, and I/D pins. **These are leakage currents when the output impedance of tristate-output and bidirectional bus pins is high.
2. Pin Capacitance
(TA = +25C) Parameter Input-pin capacitance Output-pin capacitance Non-SCSI pins Input/output-pin capacitance SCSI pins CI/O Symbol CIN COUT VDD = VIN = 0 V f = 1 MHz Measurement Conditions Requirements Unit Min. -- -- -- -- Max. 16 16 16 32 pF pF pF pF
14
MB86603
3. Loading Conditions for Measurement of AC Characteristics
(1) Non-SCSI pins
(VDD = 5 V 5%, VSS = 0 V, TA = 0C to +70C)
Measurement point Pin symbol MB86603 Measured pin
CL
CL 60pF 30pF 85pF
INT DREQ D15 to D8, UDP, D7 to D0,LDP, DMD15 to DMD8, UDMDP, DMD7 to DMD0, LDMDP
(2) SCSI pins
Measurement point
MB86603 Measured pin
RL1
Load resistance Load capacitance
RL1 = 110 RL2 = 165 CL = 200pF
RL2
CL
15
MB86603
4. AC Characteristics
(1) System clock
Limits Parameter Clock frequency Clock pulse duration (Low) Clock pulse duration (High) Clock pulse rise time Clock pulse fall time Symbol Min. tCLF tCLCL tCLCH tCR tCF 31.25 10.0 10.0 -- -- Typ. -- -- -- -- -- Max. 83.26 -- -- 10.0 10.0 ns Unit
Clock signal
tCLCH
tCLF
tCF 2.2V 0.8V 2.2V 0.8V
tCR 2.2V 0.8V 2.2V 0.8V
CLK
tCLCL
(2) System reset
Limits Parameter Reset (RESET) pulse duration at Low Symbol Min. tWRSL 4tCLF Typ. -- Max. -- ns Unit
Reset signal
TWRSL
RESET
16
MB86603 (3) MPU Interface (80 Series)
* Register write timing
Limits Parameter Address (A4 to A0), BHE setup time Address (A4 to A0) hold time CS0 setup time CS0 hold time Data setup time Data hold time WR pulse duration at Low Symbol Min. tAWS tAWH tCWS tCWH tDWS tDWH tWR 40 20 20 10 40 20 70 Max. -- -- -- -- -- -- -- ns Unit
A4 to A0 BHE tAWS tAWH
CS0
tCWS
tWR
tCWH
WR
tDWS
tDWH
D15 to D8, UDP D7 to D0, LDP
DATA
17
MB86603
* Register read timing
Limits Parameter Address (A4 to A0), BHE setup time Address (A4 to A0) hold time CS0 setup time CS0 hold time RD set Low data output defined time RD set High data output disable time RD pulse duration at Low INT signal clear time Symbol Min. tARS tARH tCRS tCRH tRLD tRHD tRD tDL 40 20 20 10 -- 5 70 -- Max. -- -- -- -- ns 70 -- -- 50 Unit
A4 to A0 BHE tARS tARH
CS0
tCRS RD
tRD
tCRH
tRLD
tRHD
D15 to D8, UDP D7 to D0, LDP
Defined data
tDL INT
18
MB86603
* Register write timing (for external access)
Limits Parameter Address (A0), BHE setup time Address (A0), BHE hold time CS1 setup time CS1 hold time WR set Low DMA bus output delay time WR set High DMA bus output undefined time MPU data bus DMA bus output delay time Symbol Min. tAWSE tAWHE tCWSE tCWHE tWLHD tWHHD tDHD 40 20 20 10 -- 5 -- Max. -- -- -- -- 70 -- 40 ns Unit
A0 BHE tAWSE tAWHE
CS1
tCWSE
tCWHE
WR
tALHD
tWHHD
D15 to D8, UDP D7 to D0, LDP
Data
tDHD
tDHD
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP
Defined data
EE EE
19
EEEE EEEE
MB86603
* Register read timing (for external access)
Limits Parameter Address (A0), BHE setup time Address (A0), BHE hold time CS1 setup time CS1 hold time RD set Low MPU data bus output enable time RD set High MPU data bus output disable time DMA bus MPU data bus output delay time Symbol Min. tARSE tARHE tCRSE tCRHE tRLNZ tRHHZ tHDD 40 20 20 10 -- 5 -- Max. -- -- -- -- 70 -- 40 ns Unit
A0 BHE tARSE tARHE
CS1
tCRSE
tCRHE
RD
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP tHDD tRLNZ
Data
tRHHZ
D15 to D8, UDP D7 to D0, LDP
20
EEEE EEEE
Defined data
MB86603 (4) MPU Interface (68 Series)
* Register write timing
Limits Parameter Address (A4 to A0) setup time Address (A4 to A0) hold time CS0 setup time CS0 hold time Data setup time Data hold time UDS/LDS pulse duration at Low R/W setup time R/W hold time Symbol Min. tAWS tAWH tCWS tCWH tDWS tDWH tDS tRWS tRWH 40 20 20 10 40 20 70 20 20 Max. -- -- -- -- -- -- -- -- -- ns Unit
A4 to A0
tAWS
tAWH
CS0
tCWS
tCWH
R/W
tRWS
tDS
tRWH
UDS/LDS
tDWS
tDWH
D15 to D8, UDP D7 to D0, LDP
Data
21
MB86603
* Register read timing
Limits Parameter Symbol Min. Address (A4 to A0) setup time Address (A4 to A0) hold time CS0 setup time CS0 hold time Data output defined time Data output disable time UDS/LDS pulse duration at Low R/W setup time R/W hold time INT signal clear time tARS tARH tCRS tCRH tRLD tRHD tDS tRWS tRWH tDH 40 20 20 10 -- 5 70 20 20 -- Max. -- -- -- -- 70 ns -- -- -- -- 50 Unit
A4 to A0 tARS tARH
CS0 tCRS tCRH
R/W tRWS tDS tRWH
UDS/LDS
tRLD
tRHD
D15 to D8, UDP D7 to D0, LDP tDH
Defined data
INT
22
MB86603
* Register write timing (for external access)
Limits Parameter Symbol Min. Address (A0) setup time Address (A0) hold time CS1 setup time CS1 hold time UDS/LDS set Low DMA bus output delay time UDS/LDS set High DMA bus output undefined time MPU data bus DMA bus output delay time R/W setup time R/W hold time tAWSE tAWHE tCWSE tCWHE tWLHD tWHHD tDHD tRWS tRWH 40 20 20 10 -- 5 -- 20 20 Max. -- -- -- -- 70 -- 40 -- -- ns Unit
A0 tAWSE tAEHE
CS1 tCASE tCWHE
R/W tRWS tDS tRWH
UDS/LDS
tWLHD D15 to D8, UDP D7 to D0, LDP
tWHHD
Data tDHD
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP
Defined data
EEE EEE
23
EEE EEE
MB86603
* Register read timing (for external access)
Limits Parameter Symbol Min. Address (A0) setup time Address (A0) hold time CS1 setup time CS1 hold time UDS/LDS set Low MPU data bus output enable time UDS/LDS set High MPU data bus output disable time DMA bus MPU data bus output delay time R/W setup time R/W hold time tARSE tARHE tCRSE tCRHE tRLNZ tRHHZ tHDD tRWS tRWH 40 20 20 10 -- 5 -- 20 20 Max. -- -- -- -- 70 -- 40 -- -- ns Unit
A0 tARSE tARHE
CS1 tCRSE tCRHE
R/W tRWS tRWH
UDS/LDS
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP tHDD tRLNZ D15 to D8, UDP D7 to D0, LDP
Data
tRHHZ
24
EEE EEE
Defined data
MB86603 (5) DMA Interface
DMA access timing The time regulations are not applicable in the following cases:
* During SCSI input and when data buffer EMPTY, or when one byte held * During SCSI output and when data buffer FULL, or when 63 bytes held * When parity error detected (target) * When error stopping transfer occurs in SCSI interface
[Burst mode (for 80 series and 68 series)]
* Access cycle time
Limits Parameter Access cycle time 1 Access cycle time 2 Access cycle time 3 Symbol Min. tDCY1 tDCY2 tDCY3 2tCLF 3tCLF 4tCLF Max. -- -- -- ns Unit
IOWR/IORD DMUDS/DMLDS tDCY1 tDCY3
tDCY2
25
MB86603
[Burst mode for 80 series]
* Write timing
Limits Parameter DREQ set High DACK set Low IOWR set Low DREQ set Low DREQ set Low DREQ set High DACK set Low IOWR set Low DMBHE, DMA0 setup time IOWR pulse duration at Low IOWR set High DACK set High DMBHE, DMA0 hold time Input data setup time Input data hold time Symbol Min. tDHAL tALDL tDLDH tALWL tDAWS tDWR tWHAH tDAWH tDDWS tDDWH 0 -- 0 0 20 40 0 20 30 10 Max. -- 35 -- -- -- ns -- -- -- -- -- Unit
tDLDH
DREQ tDHAL tALDL
DACK
tALWL
tWHAH
DMBHE DMA0 tDAWS IOWR tDWR tDAWH
tDDWS DMD15 to DMD0 UDMDP, LDMDP
tDDWH
Data
26
MB86603
* Read timing
Limits Parameter DREQ set High DACK set Low IORD set Low DREQ set Low DREQ set Low DREQ set High DACK set Low IORD set Low DMBHE, DMA0 setup time IODR pulse duration at Low IODR set High DACK set High DMBHE, DMA0 hold time Data output defined time Data output hold time Symbol Min. tDHAL tALDL tDLDH tALRL tDARS tDRD tRHAH tDARH tDRLD tDRHD 0 -- 0 0 20 40 0 20 -- 5 Max. -- 35 -- -- -- ns -- -- -- 40 -- Unit
tDLDH
DREQ tDHAL tALDL
DACK
tALRL
tRHAH
DMBHE DMA0 tDARS IORD tDRD tDARH
tDRLD DMD15 to DMD0 UDMDP, LDMDP
tDRHD
Defined data
27
MB86603
[Burst mode for 68 series]
* Write timing
Limits Parameter DREQ set High DACK set Low DMUDS/DMLDS set Low DREQ set Low DREQ set Low DREQ set High DACK set Low DMUDS/DMLDS set Low DMR/W setup time DMUDS/DMLDS pulse duration at Low DMUDS/DMLDS set High DACK set High DMR/W hold time Input data setup time Input data hold time Symbol Min. tDHAL tALDL tDLDH tALDL tDRWS tDDS tDHAH tDRWH tDDWS tDDWH 0 -- 0 10 20 40 0 20 30 10 Max. -- 35 -- -- -- ns -- -- -- -- -- Unit
tDLDH
DREQ tDHAL tALDL
DACK
tALDL tDHAH DMR/W
DMUDS/DMLDS
tDRWS
tDDS
tDRWH
tDDWS DMD15 to DMD0 UDMDP, LDMDP
tDDWH
Data
28
MB86603
* Read timing
Limits Parameter DREQ set High DACK set Low DMUDS/DMLDS set Low DREQ set Low DREQ set Low DREQ set High DACK set Low DMUDS/DMLDS set Low DMR/W setup time DMUDS/DMLDS pulse duration at High DMUDS/DMLDS set High DACK set High DMR/W hold time Output data defined time Output data hold time Symbol Min. tDHAL tALDL tDLDH tALDL tDRWS tDDS tDHAH tDRWH tDRLD tDRHD 0 -- 0 10 20 40 0 20 -- 5 Max. -- 35 -- -- -- ns -- -- -- 40 -- Unit
tDLDH
DREQ tDHAL tALDL
DACK
tALDL
tDHAH
DMR/W
tDRWS DMUDS/DMLDS
tDDS
tDRWH
tDRLD DMD15 to DMD0 UDMDP, LDMDP
tDRHD
Defined data
29
MB86603 (6) SCSI Interface (Initiator)
[Asynchronous transfer mode]
* Input timing (target initiator)
Limits Parameter ACK set Low REQ set High REQ set High ACK set High ACK set High REQ set Low Data bus defined REQ set Low REQ set Low data bus hold time REQ set Low ACK set Low REQ set High ACK set Low* Symbol Min. tAOLR tRAOH tAOHR tDTSU tDHLD tRAOL tRACY 0 -- 10 10 20 -- -- Max. -- 60 -- -- -- 40 3tCLF + 40 ns Unit
*The time (tRACY) of REQ set High ACK set Low is set to the longer time compared to (tRAOH + tAOHR + tRAOL). Note: The input timing regulations are not applicable in the following cases. * When data register FULL in data phase
* When last byte transferred
tRACY REQ
tAOLR ACK
tRAOH
tAOHR
tRAOL
tDTSU
tDHLD
DB7 to DB0, LDBP DB15 to DB8, UDBP
Data
30
MB86603
* Output timing (initiator target)
Limits Parameter ACK set Low REQ set High REQ set High ACK set High ACK set High REQ set Low Data bus output defined ACK set Low* REQ set High data bus hold time REQ set Low ACK set Low Symbol Min. tAOLR tRAOH tAOHR tDVLD tDIVD tRAOL 0 -- 10 S*tCLF - 10 2tCLF -- Max. -- 60 -- ns -- -- 40 Unit
*The value of S varies with the setting condition of the asynchronous setup time register (address 23). Note: The output timing regulations are not applicable when the data register is EMPTY in the data phase.
tRACY* REQ
tAOLR ACK
tRAOH
tAOHR
tRAOL
tDVLD
tDIVD
tDVLD
DB7 to DB0, LDBP DB15 to DB8, UDBP
*The time (tRACY) of REQ set High ACK set Low is set to the longer time of either (tRAOH + tAOHR + tRAOL) or (tDIVD + tDVLD).
EEE EEE
Defined Data
Defined Data
31
MB86603
[Synchronous transfer mode]
* REQ/ACK signal synchronization
Limits Parameter Symbol Min. ACK Assertion Period* ACK Negation Period* REQ Assertion Period REQ Negation Period REQ input cycle time (1) REQ input cycle time (2) tAKAP tANAP tRQAP tRNAP tRQF1 tRQF2 A*tCLF - 3 N*tCLF - 3 20 20 1tCLF 3tCLF Max. -- -- -- ns -- -- -- Unit
*The values of A and N vary with the setting condition of the transfer period register (address 13).
tAKAP ACK
tANAP
tRQAP
tRNAP
REQ tRQF1 tRQF2
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MB86603
* Input timing (target initiator)
Limits Parameter Data bus defined REQ set Low REQ set Low data bus hold time Symbol Min. tDTSU tDHLD 10 20 Max. -- ns -- Unit
REQ
tDTSU
tDHLD
tDTSU
tDHLD
DB7 to DB0, LDBP DB15 to DB8, UDBP
Data
Data
* Output timing (initiator target)
Limits Parameter Data bus defined ACK set Low* ACK set Low data bus hold time* Symbol Min. tDVAK tAKDH N*tCLF - 5 A*tCLF - 5 Max. -- ns -- Unit
*The values of A and N vary with the setting condition of the transfer period register (address 13).
ACK
tDVAK DB7 to DB0, LDBP DB15 to DB8, UDBP
tAKDH
tDVAK
tAKDH
Defined data
Defined data
EEEE EEEE
33
EE EE
EEEE EEEE
MB86603 (7) SCSI Interface (Target)
[Asynchronous transfer mode]
* Input timing (initiator target)
Limits Parameter REQ set Low ACK set Low ACK set Low REQ set High REQ set High ACK set Low Data bus defined ACK set Low ACK set Low data bus hold time ACK set High REQ set Low ACK set Low REQ set Low* Symbol Min. tRDLA tAKOH tROHA tVTSU tDHLD tAROL tRACY 0 -- 0 10 20 -- -- Max. -- 60 -- -- -- 40 3tCLF + 40 ns Unit
*The time (tRACY) of ACK set Low REQ set Low is set to the longer time compared with (tAROH + tROHA + tAROL). Note: The input timing regulations are not applicable when the data register is FULL in the data phase.
tRACY REQ tROLA ACK tAROH tROHA tAROL
tDTSU DB7 to DB0, LDBP DB15 to DB8, UDBP
tDHLD
Data
34
MB86603
* Output timing (target initiator)
Limits Parameter REQ set Low ACK set Low ACK set Low REQ set High REQ set High ACK set High Data bus output defined REQ set Low* ACK set Low data bus hold time ACK set High REQ set Low Symbol Min. tROLA tAROH tROHA tDVLD tDIVD tAROL 0 -- 0 S*tCLF - 10 2tCLF -- Max. -- 60 -- ns -- -- 40 Unit
*The value of S varies with the setting condition of the asynchronous setup time register (address 23). Note: The output timing regulations are not applicable when the data register is EMPTY in the data phase.
tRACY* REQ tROLA ACK tAROH tROHA tAROL
tDVLD DB7 to DB0, LDBP DB15 to DB8, UDBP
tDIVD Defined data
tDVLD Defined data
*The time (tRACY) of ACK set Low REQ set Low is set to the longer time of either (tAROH + tROHA + tAROL) or (tDIVD + tDVLD).
EEE EEE
35
MB86603
[Synchronous transfer mode]
* REQ/ACK signal synchronization
Limits Parameter REQ Assertion Period* REQ Negation Period* ACK Assertion Period ACK Negation Period ACK input cycle time (1) ACK input cycle time (2) Symbol Min. tRQAP tRNAP tAKAP tANAP tAKF1 tAKF2 A*tCLF - 3 N*tCLF - 3 20 20 1tCLF 3tCLF Max. -- -- -- ns -- -- -- Unit
*The values of A and N vary with the setting condition of the transfer period register (address 13).
tRQAP REQ
tRNAP
tAKAP
tANAP
ACK tAKF1 tAKF2
36
MB86603
* Input timing (initiator target)
Limits Parameter Data bus defined ACK set Low ACK set Low data bus hold time Symbol Min. tDTSU tDHLD 10 20 Max. -- ns -- Unit
ACK
tDTSU
tDHLD
tDTSU
tDHLD
DB7 to DB0, LDBP DB15 to DB8, UDBP
Data
Data
* Output timing (target initiator)
Limits Parameter Data bus defined REQ set Low* REQ set Low data bus hold time* Symbol Min. tDVRQ tRQDH N*tCLF - 5 A*tCLF - 5 Max. -- ns -- Unit
*The values of A and N vary with the setting condition of the transfer period register (address 13).
REQ
tDVRQ DB7 to DB0, LDBP DB15 to DB8, UDBP
tRQDH
tDVRQ
tRQDH
Defined data
Defined data
EEEE EEEE
37
EE EE
EEEE EEEE
MB86603 (8) A, N, and S Values in SCSI Interface Timing Specifications
* Set values and A and N values of transfer period register
Transfer period register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A N Transfer period register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 N 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16
(Inhibited) (Inhibited) 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8
The A and N values in the register setting represent the assertion and negation periods (in clock-cycle units). The numerical value is applicable to the A and N values in AC characteristics.
38
MB86603
* Set values and S values of asynchronous setup time setting register
Asynchronous setup time setting register Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S
The S (setup time) value of the setup time setting register in asynchronous data transfer represents the time required to assert the REQ or ACK signal after setting data at the data bus (in clock-cycle units). The numerical value is applicable to the S value in AC characteristics.
39
MB86603
REGISTER LIST
1. BASIC Control Register (At Write)
Address Registe Name Decimal A4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SCSI output data register SCSI output data register Direct control register (Reserved) SEL/RESEL-ID register Command register Data block register (MSB) Data block register (LSB) Data byte register (MSB) Data byte register Data byte register (LSB)/MC byte register Diagnostic control signal register Transfer mode register Transfer period register Transfer offset register Window address register WA7 WA6 SI7 CM7 CM6 CM5 CM4 SI3 CM3 SI2 CM2 SI1 CM1 BL9 BL1 SI0 CM0 BL8 BL0 Bit 7 DO7 Bit 6 DO6 Bit 5 DO5 Bit 4 DO4 Bit 3 DO3 Bit 2 DO2 Bit 1 DO1 Bit 0 DO0 DO8 DC0 Bit Assignment
DO15 DO14 DO13 DO12 DO11 DO10 DO9 DC7
BL15 BL14 BL13 BL12 BL11 BL10 BL7 BL6 BL5 BL4 BL3 BL2
BY23 BY22 BY21 BY20 BY19 BY18 BY17 BY16 BY15 BY14 BY13 BY12 BY11 BY10 BY7 DG7 TM7 BY6 DG6 TM6 TP4 TO4 WA4 TP3 TO3 WA3 TP2 TO2 WA2 TP1 TO1 WA1 TP0 TO0 WA0 BY5 DG5 BY4 BY3 DG3 BY2 DG2 BY9 BY1 DG1 BY8 BY0 DG0
40
MB86603
2. BASIC Control Register (At Read)
Address Registe Name Decimal A4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SCSI input data register SCSI input data register SPC status register Nexus status register Interrupt status register Command step register Data block register (MSB) Data block register (LSB) Data byte register (MSB) Data byte register Data byte register (LSB)/MC byte register SCSI control signal status register Transfer mode register Transfer period register Transfer offset register Modifier byte register MB6 MB5 Bit 7 DI7 DI15 SS7 NS7 IS7 CS7 Bit 6 DI6 DI14 SS6 NS6 IS6 CS6 IS5 CS5 IS4 CS4 Bit 5 DI5 DI13 SS5 Bit 4 DI4 DI12 Bit 3 DI3 DI11 SS3 NS3 IS3 CS3 Bit 2 DI2 DI10 SS2 NS2 IS2 CS2 Bit 1 DI1 DI9 SS1 NS1 IS1 CS1 BL9 BL1 Bit 0 DI0 DI8 SS0 NS0 IS0 CS0 BL8 BL0 Bit Assignment
BL15 BL14 BL13 BL12 BL11 BL10 BL7 BL6 BL5 BL4 BL3 BL2
BY23 BY22 BY21 BY20 BY19 BY18 BY17 BY16 BY15 BY14 BY13 BY12 BY11 BY10 BY7 SC7 TM7 BY6 SC6 TM6 TP4 TO4 MB4 TP3 TO3 MB3 TP2 TO2 MB2 TP1 TO1 MB1 TP0 TO0 MB0 BY5 SC5 BY4 SC4 BY3 SC3 BY2 SC2 BY9 BY1 SC1 BY8 BY0 SC0
41
MB86603
3. Initialization Window (At Write and Read)
Address Registe Name Decimal A4 16 17 18 19 20 21 22 23 24 25 26 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 1 0 1 0 Clock conversion setting register Self-ID setting register Response operation mode setting register SEL/RESEL operation mode setting register SEL/RESEL retry setting register SEL/RESEL timeout setting register REQ/ACK timeout setting register Asynchronous setup time setting register Parity error detection setting register Interrupt enable setting register Group 6/7 command-length setting register PE7 IE7 GL7 GL6 PE6 PE5 IE5 GL5 PE4 IE4 GL4 AM7 SM7 SR7 ST7 RT7 AM6 SM6 SR6 ST6 RT6 AM5 SM5 SR5 ST5 RT5 AM4 SM4 SR4 ST4 RT4 SM3 SR3 ST3 RT3 AT3 PE3 IE3 GL3 IE2 GL2 SM2 SR2 ST2 RT2 AT2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CC3 OI3 Bit 2 CC2 OI2 Bit 1 CC1 OI1 AM1 SM1 SR1 ST1 RT1 AT1 PE1 IE1 GL1 Bit 0 CC0 OI0 AM0 SM0 SR0 ST0 RT0 AT0 PE0 IE0 GL0 Bit Assignment
42
MB86603
4. MCS Buffer Window
Address At Write Decimal A4 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer At Read
43
MB86603
5. User Program Memory Window
Address At Write Decimal A4 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory At Read
44
MB86603
COMMAND LIST
The SPC commands can be set to the command register and user program memory. The commands can be classified as follows depending on the setting methods.
* Sequential command
This command performs the continuous sequential operations (including phase changes). It can be set only at the command register.
* Discrete command
This command performs the discrete operations of the sequential command. It can be set at both the command register and user program memory.
* Special command
This command is used to perform operations with the user program. It can be set only at the user program memory. Setting Setting at command register Common type Sequential command (1-byte command) Discrete command (1-byte command) Special command (1- or 2-byte command) : Setting possible : Setting impossible (1- or 2-byte command) Setting at command register
45
MB86603
1. Initiator Command
(1) Sequential command
No 1 2 3 4 5 6 7 8 00H 01H 02H 03H 04H 05H 06H 07H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Command Code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Operand (When program executed) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) Command Name SELECT & CMD SELECT & 1-MSG & CMD SELECT & N-Byte-MSG & CMD SELECT & 1-MSG SELECT & N-Byte-MSG SEND N-Byte-MSG SEND N-Byte-CMD RECEIVE N-Byte-MSG
(2) Discrete command
No 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 08H 09H 0AH 0BH 0CH 0DH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Command Code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Operand (When program executed) -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address of issued message Address of issued message Address where message written Address of issued command Address where status written SELECT SELECT with ATM SET ATN RESET ATN SET ACK RESET ACK SEND DATA from MPU SEND DATA from DMA RECEIVE DATA to MPU RECEIVE DATA to DMA SEND DATA from MPU (Padding) SEND DATA from DMA (Padding) RECEIVE DATA to MPU (Padding) RECEIVE DATA to DMA (Padding) SEND 1-MSG SEND 1-MSG with ATN RECEIVE MSG SEND CMD RECEIVE STATUS Command Name
46
MB86603
2. Target Command
(1) Sequential command
No 1 2 3 20H 21H 22H 0 0 0 0 0 0 Command Code 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Operand (When program executed) (Impossible) (Impossible) (Impossible) Command Name RESELECT & 1-MSG RESELECT & N-Byte-MSG RESELECT & 1-MSG & TERMINATE RESELECT & 1-MSG & LINK TERMINATE TERMINATE LINK TERMINATE DISCONNECT SEQUENCE SEND N-Byte-MSG RECEIVE N-Byte-CMD RECEIVE N-Byte-MSG RESELECT & N-Byte-MSG & TERMINATE RESELECT & N-Byte-MSG & LINK TERMINATE DISCONNECT SEQUENCE 2
4 5 6 7 8 9 10 11
23H 24H 25H 26H 27H 28H 29H 2AH
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0
(Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible)
12 13
2BH 2CH
0 0
0 0
1 1
0 0
1 1
0 1
1 0
1 0
(Impossible) (Impossible)
(2) Discrete command
No 14 15 16 17 18 19 20 21 22 23 24 25 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Command Code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Operand (When program executed) -- -- -- -- -- -- -- -- Address of issued message Address where message written Address of issued status Address where CDB* written Command Name RESELECT SET REQ RESET REQ DISCONNECT SEND DATA from MPU SEND DATA from DMA RECEIVE DATA to MPU RECEIVE DATA to DMA SEND 1-MSG RECEIVE MSG SEND STATUS RECEIVE CMD
*CDB = Command Descriptor Block
47
MB86603
3. Common Command
No 1 2 3 4 5 6 7 8 40H 41H 42H 43H 44H 45H 46H 47H 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Command Code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Operand (When program executed) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) (Impossible) Command Name SOFYWARE RESET TRANSFER RESET SCSI RESET SET UP REG INIT DIAG START TARG DIAG START DIAG END COMMAND PAUSE
4. Programmable Command
The user program is preset to the user program memory and starts operation when the starting address of the user program memory is written to the command register. The programmable command has discrete and special commands and is 1- or 2-bytes long. The command field assignment is given in the following table.
* Command field assignment
Command Code (First Byte) Send command in message, command, and status phases Discrete command Receive command in message, command, and status phases Command for disallowing receive/send command and transfer in data phase AND command TEST AND command COMPARE command Special command Conditional-branch IF-GOTO command MOVE command STOP command NOP command Jump address Memory address to be moved User status code -- Operand (Second Byte) Memory address where sent data exists Memory address where received data stored
-- Data for AND operation or memory address where data for AND operation exists Data for AND operation or memory address where data for AND operation exists Data for comparison operation or memory address where data for comparison operation exists
48
MB86603
SYSTEM CONFIGURATION
1. 80-Series Separate Bus Type
Differential driver/receiver MB86603 Oscillator circuit CLK RESET
Reset circuit
DB15 to 8 UDBP DB7 to 0 LDBP
MODE DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP INT MPU
ACK ATN INIT
CS0 CS1
Address decoder
A4 to A0 REQ MSG C/D I/O TARG D15 to D0 UDP LDP BHE RD WR DMD15 to 0 UDMDP BSY BSYOE LDMDP
Address bus
Data bus
DMA bus
SEL SELOE
DREQ DACK DMBHE IORD IOWR DMA controller Address Data buffer memory
RST RSTOE
DMA0 TP
S/DSEL
49
MB86603
2. 80-Series Common Bus Type
Differential driver/receiver MB86603 Oscillator circuit CLK RESET
Reset circuit
DB15 to 8 LDBP DB7 to 0 UDBP
MODE DBOE15 to 8 LDBOEP DBOE7 to 0 UDBOEP INT MPU
ACK ATN INIT
CS1 CS0
Address decoder
A4 to A0 REQ MSG C/D I/O TARG D15 to D0 UDP LDP BHE RD WR DMD15 to 0 UDMDP BSY BSYOE LDMDP
Address bus
Data bus
DMA bus
SEL SELOE
DREQ DACK DMA controller DMBHE IORD IOWR
RST RSTOE
DMA0 TP
S/DSEL
50
MB86603
3. 68-Series Separate Bus Type
Differential driver/receiver MB86603 Oscillator circuit CLK RESET MODE
Reset circuit
DB15 to 8 UDBP DB7 to 0 LDBP DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP
INT MPU A0 CS0 CS1
ACK ATN INIT
Address decoder
A4 to A0 REQ MSG C/D I/O TARG D15 to D0 UDP LDP R/W UDS LDS DMD15 to 0 UDMDP BSY BSYOE LDMDP
Address bus
Data bus
DMA bus
SEL SELOE
DREQ DACK DMR/W DMUDS DMLDS . DMA controller Address Data buffer memory
RST RSTOE
DMA0 S/DSEL TP
51
MB86603
4. 68-Series Common Bus Type
Differential driver/receiver MB86603 Oscillator circuit CLK RESET MODE
Reset circuit
DB15 to 8 LDBP DB7 to 0 UDBP DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP
INT MPU A0 CS1 CS0
ACK ATN INIT
Address decoder
A4 to A0 REQ MSG C/D I/O TARG D15 to D0 UDP LDP R/W UDS LDS DMD15 to 0 UDMDP BSY BSYOE LDMDP
Address bus
Data bus
DMA bus
SEL SELOE
DREQ DACK DMA controller DMR/W DMUDS DMLDS .
RST RSTOE
DMA0 S/DSEL TP
52
MB86603
5. Example of Connection in Differential Mode (Example of Driver/Receiver Connection)
(TOP VIEW)
RO RE DE DI
1 R 2 3 4 D
8 7 6 5
VCC DO, RI DO, RI GND
MB561 SCSI bus MB86603 DB15 to 0 UDBP LDBP 18 DBOE15 to 0 UDBOEP LDBOEP (-) SIGNAL D 18 R
(+) SIGNAL
2 ACK, ATN R (+) SIGNAL
INIT D
(-) SIGNAL
4 REQ, MSG C/D, I/O R (+) SIGNAL
TARG D
(-) SIGNAL
3 BSY, SEL RST R 3 BSYOE, SELOE RSTOE D S/DSEL (-) SIGNAL
(+) SIGNAL
53
MB86603
6. Example of Connection in Single-end Mode
MB86603 18 DB15 to 0 UDBP LDBP 18 DBOE15 to 0 UDBOEP LDBOEP (OPEN)
SCSI bus
2 ACK, ATN
INIT
(OPEN)
4 REQ, MSG C/D, I/O
TARG
(OPEN)
3 BSY, SEL RST
3 BSYOE, SELOE RSTOE (OPEN)
S/DSEL
54
MB86603
PACKAGE DIMENSIONS
176-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-176P-M01)
132 133
1.047 .008 SQ (26.60 0.20) .954 .004 SQ (24.00 0.10)
.152 (3.85) MAX (MOUNTING HEIGHT)
89 88
0 (0) MIN (STAND OFF HEIGHT)
1.008 (25.60) NOM .846 (21.50) REF
INDEX
"A"
45
176
LEAD No.
1
44
.0197 (0.50) TYP
.008 .004 (0.20 0.10)
.003 (0.08)
M
.006 .002 (0.15 0.05) Details of "A" part .010 (0.25) .008 (0.20) .006 (0.15) MAX .016 (0.40) MAX Details of "B" part
"B"
.004 (0.10)
0 to 10 .020 .008 (0.50 0.20)
(c)1992 FUJITSU LIMITED F176001S-3C
Dimensions in inches (millimeters)
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.
55
MB86603
For further information please contact: Japan FUJITSU LIMITED Electronic Devices International Operations Department KAWASAKI PLANT, 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211, Japan Tel: (044) 754-3753 FAX: (044) 754-3332 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 FAX: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10, 63303 Dreieich-Buchschlag, Germany Tel: (06103) 690-0 FAX: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LIMITED No.51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 0718 Tel: 336-1600 FAX: 336-1609
I9411 (c) FUJITSU LIMITED Printed in Japan
56

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